82830MP Datasheet, PDF (111/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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5.2.4.11
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259-
compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction,
except that the address bus does not contain a valid address.
Interrupt Acknowledge cycle is always directed to the hub interface (never to AGP/PCI).
5.2.4.12
Locked Cycles
The GMCH-M supports resource locking due to the assertion of the LOCK# line on the CPU bus as
follows.
5.2.4.12.1
CPU<->System SDRAM Locked Cycles
The GMCH-M supports CPU to SDRAM locked cycles. The host bus may not execute any other
transactions until the locked cycle is complete. The GMCH-M arbiter may grant another hub interface
or AGP device, but any “Coherent” cycles to SDRAM will be blocked. CPU Lock operations DO NOT
block any “Non_Coherent” accesses to SDRAM.
5.2.4.12.2
CPU<->Hub Interface Locked Cycles
Any CPU-to-hub interface locked transaction will initiate a hub interface locked sequence. The P6 bus
implements the bus lock mechanism, which means that no change of bus ownership can occur from the
time one agent, has established a locked transaction (i.e., the initial read cycle of a locked transaction has
completed) until the locked transaction is completed. Note that for CPU-to-hub interface lock
transactions, a bit in the request packet indicates a lock transaction.
Any concurrent cycle that requires snooping on the host bus is not processed while a LOCK transaction
is occurring on the host bus.
Hub interface-to-SDRAM locked cycles are not supported.
5.2.4.12.3
CPU<->AGP/PCI Locked Cycles
The AGP/PCI1 interface does not support locked operations and therefore both CPU locked and non-
locked transactions destined to AGP/PCI1 are propagated in the same manner. However, note that any
concurrent cycle that requires snooping on the host bus is not processed while a LOCK transaction is
occurring on the host bus.
5.2.4.13
Branch Trace Cycles
An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. Address
Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear address of the
instruction causing the branch and D[31:0]# carries the target linear address. The GMCH-M will respond
and retire this transaction but will not latch the value on the data lines or provide any additional support
for this type of cycle.
5.2.4.14
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. In the first address phase
Aa[35:3]# is undefined and can be driven to any value. In the second address phase, Ab[15:8]# defines
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Datasheet
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