82830MP Datasheet, PDF (67/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
Bit
Description
10:8
Refresh Mode Select (RMS): Bits Determine if Refresh is enabled and Refresh Rate.
000: Refresh Disabled.
001: Refresh Enabled. Refresh interval 15.6 µs.
010: Refresh Enabled. Refresh interval 7.8 µs.
011: Reserved
111: Refresh Enabled. Refresh interval 128 Clocks. (Fast Refresh Mode)
All Other Combinations are reserved.
Default Value=000.
7
Reserved
6:4
Mode Select (SMS). These bits select the special operational mode of the GMCH-M SDRAM interface. The
special modes are intended for initialization at power up.
000 = Self refresh (Default). In this mode CKEs are de-asserted. All other values cause CKE assertion. The
exception is in C3/S1/S3 this register is programmed to “normal operation”, the DRAMs are in self-refresh,
and CKEs are de-asserted.
001 = NOP Command Enable. In this mode all CPU cycles to SDRAM result in a NOP Command on the
SDRAM interface.
010 = All Banks Pre-charge Enable. In this mode all CPU cycles to SDRAM result in an All Banks Pre-charge
Command on the SDRAM interface.
011 = Mode Register Set Enable. In this mode all CPU cycles to SDRAM result in a mode register set
command on the SDRAM interface. The Command is driven on the MA[12:0] lines. MA[2:0] must always be
driven to 010 for burst of 4 mode. MA3 must be driven to 1 for interleave wrap type.
MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field.
CAS Latency
MA[6:4]
2 Clocks
010
3 Clocks
011
MA[12:7] must be driven to 00000.
BIOS must calculate and drive the correct host address for each row of memory such that the
command is driven on the MA[12:0] lines.
correct
100 = Reserved.
101 = Reserved.
110 = CBR Refresh Enable. In this mode all CPU cycles to SDRAM result in a CBR cycle on the SDRAM
interface.
111 = Normal Operation.
Default Value=000.
3:2
Reserved.
1:0
Reserved.
298338-001
Datasheet
67