82830MP Datasheet, PDF (88/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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4.5.2.6
SUBC1 - Sub-Class Code Register - Device #1
Address Offset:
Default Value:
Access:
Size:
0Ah
04h
Read Only
8 bits
This register contains the Sub-Class Code for the GMCH-M device #1. This code is 04h indicating a
PCI-PCI Bridge device. The register is read only.
Bit Description
7:0 Sub-Class Code (SUBC1). This is an 8-bit value that indicates the category of Bridge into which the
GMCH-M falls. The code is 04h indicating a Host Bridge.
Default Value=0000/0100.
4.5.2.7
BCC1 - Base Class Code Register - Device #1
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class Code of the GMCH-M device #1. This code is 06h indicating a
Bridge device. This register is read only.
Bit Description
7:0 Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH-M
device #1. This code has the value 06h, indicating a Bridge device.
Default Value=00000110.
4.5.2.8
MLT1 - Master Latency Timer Register - Device #1
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read/Write
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
Bit Description
7:3 Not applicable but support read/write operations. (Reads return previously written data.)
Default Value=00000.
2:0 Reserved.
88
Datasheet
298338-001