82830MP Datasheet, PDF (122/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
5.4.8.3
5.4.8.4
Source Bus
Command
Other Encoded Information
GMCH-M Host Bridge
Corresponding
PCI1 Command
C/BE[3:0]#
Encoding
Memory Write
Length = 16 Bytes
None
N/A
Length = 32 Bytes
Memory Write
0111
Locked Access
All combinations
Unlocked Access¹
As Applicable
Reserved Encodings
All Combinations
None
N/A
EA Memory Access
Address ≥ 4 GB
None
N/A
Source Bus: hub interface
Memory Write
-
Memory Write
0111
NOTES:
1. CPU to AGP/PCI1 bus can result in deadlocks. Locked access to AGP/PCI1 bus is strongly discouraged.
2. N/A refers to a function that is not applicable. Not Supported refers to a function that is available but specifically
not implemented on GMCH-M.
As an initiator of AGP/PCI1 cycle, the GMCH-M only supports the following transactions:
Memory Read - All CPU to AGP/PCI1 reads will use the Memory Read command.
Memory Write - GMCH-M initiates AGP/PCI1 cycles on behalf of the CPU or hub interface. GMCH-
M does not issue Memory Write and Invalidate as an initiator. GMCH-M does not support
write merging or write collapsing. GMCH-M will combine CPU-to-PCI writes (Dword or
Qword) to provide bursting on the AGP/PCI1 bus. GMCH-M allows non-snoopable write
transactions from hub interface to the AGP/PCI1 bus.
I/O Read and Write - I/O read and write from the CPU are sent to the AGP/PCI1 bus. I/O base and
limit address range for PCI1 bus are programmed in AGP/PCI1 configuration registers. All
other accesses that do not correspond to this programmed address range are forwarded to hub
interface.
Exclusive Access - GMCH-M will not issue a locked cycle on AGP/PCI1 bus on the behalf of either
the CPU or hub interface. Hub interface and CPU locked transactions to AGP/PCI1 will be
initiated as unlocked transactions by the GMCH-M on the AGP/PCI1 bus.
Configuration Read and Write - Host Configuration accesses to internal GMCH-M registers are
driven onto AGP/PCI1 as Type 1 Configuration Cycles where they are then claimed by the
GMCH-M. This is done to support co-pilot mode. Host Configuration cycles to AGP/PCI1
are forwarded as Type 1 Configuration Cycles.
GMCH-M Retry/Disconnect Conditions
The GMCH-M generates retry/disconnect according to the AGP Specification rules when being accessed
as a target from the AGP interface (using PCI semantics).
Delayed Transaction
When an AGP/PCI-to-SDRAM read cycle is retried by the GMCH-M it will be processed internally as a
Delayed Transaction.
The GMCH-M supports the Delayed Transaction mechanism on the AGP target interface for the
transactions issued using PCI semantics. This mechanism is compatible with the PCI 2.2 Specification.
122
Datasheet
298338-001