82830MP Datasheet, PDF (18/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
3 Signal Description
This section provides a detailed description of the Intel 82830MP GMCH-M signals. The signals are
arranged in functional groups according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
When not otherwise specified, “set” refers to changing a bit to its asserted state (a logical 1). Clear
refers to changing a bit to its negated state (a logical 0). The following notations are used to describe the
signal type:
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
s/t/s
Sustained Tristate. This pin is driven to its inactive state prior to tri-stating.
as/t/s
Active Sustained Tristate. This applies to some of the Hub interface signals. This pin
is weekly driven to its last driven value.
The signal description also includes the type of buffer used for the particular signal:
AGTL
Open Drain 1.25V AGTL interface signal. Refer to the AGTL+ I/O Specification for
complete details. AGTL+ signals are “inverted bus” style where a low voltage
represents a logical “1”.
AGP/1.5V
Signals used for AGP or 1.5V interfaces. AGP signals are compatible with AGP 2.0
1.5V Signaling Environment DC and AC Specifications. The buffers are not 3.3V
tolerant.
LVTTL
Low Voltage TTL compatible signals. These are also 3.3V outputs.
CMOS
CMOS buffers.
Note that CPU address and data bus signals are logically inverted signals. In other words, the actual
values are inverted of what appears on the CPU bus. This must be taken into account and the addresses
and data bus signals must be inverted inside the GMCH-M. All CPU control signals follow normal
convention. A 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1
indicates an active level (high voltage) if the signal has no # suffix.
Table 1 shows the Vtt/Vdd and Vref levels for the various interfaces.
18
Datasheet
298338-001