82830MP Datasheet, PDF (104/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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BIOS or system designer’s responsibility to limit SDRAM population so that adequate PCI, AGP, High
BIOS, and APIC memory space can be allocated.
15 MB-16 MB Window
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable (FDHC register) in Device
0 space. Accesses within this hole are forwarded to the hub interface. The range of physical SDRAM
memory disabled by opening the hole is not remapped to the Top of the memory – that physical
SDRAM space is not accessible. This 15 MB-16 MB hole is an optionally enabled ISA hole. Video
accelerators originally used this hole. Validation and customer SV teams also use it for some of their
test cards. That is why it is being supported. There is no inherent BIOS request for the 15-16 hole.
Pre-allocated Memory
Physical addresses that are not accessible as general system memory and reside within system memory
address range (less than TOM) are created for SMM-mode and legacy VGA graphics compatibility. The
Intel 830MP supports an increased amount of pre-allocated memory to support up to
1600X1200X32bpp. The pre-allocated memory allows sizes of 512 KB, 1 MB, or 8 MB. For VGA
graphics compatibility, pre-allocated memory is only required in non-local memory configurations. The
system BIOS must properly initialize these regions.
Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG
SMM-mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM-
mode CPU accesses to enabled HSEG are considered invalid and are terminated immediately on the host
interface. The exceptions to this rule are Non-SMM-mode Write Back cycles that are remapped to SMM
space to maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are
not allowed. Physical SDRAM behind the HSEG transaction address is not remapped and is not
accessible.
TSEG
TSEG can be up to 1 MB in size and is at the top of physical memory. SMM-mode CPU accesses to
enabled TSEG access the physical SDRAM at the same address. Non-SMM-mode CPU accesses to
enabled TSEG is considered invalid and are terminated immediately on the host interface. The
exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical SMM
space to maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are
not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When the
extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this range are
forwarded to the hub interface. When SMM is enabled the amount of memory available to the system is
equal to the amount of physical SDRAM minus the value in the TSEG register.
PCI Memory Address Range (Top of Main Memory to 4 GB)
The address range from the top of main SDRAM to 4 GB (top of physical memory space supported by
the GMCH-M) is normally mapped via the hub interface to PCI.
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Datasheet
298338-001