82830MP Datasheet, PDF (26/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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3.3.5 PCI Signals - AGP Semantics
PCI signals are redefined when used in AGP transactions that are carried using AGP protocol extension.
For transactions on the AGP interface that are carried using PCI protocol, these signals completely
preserve PCI 2.2 semantics. The exact roles of all PCI signals during AGP transactions are defined
below.
Table 8. PCI Signals – AGP Semantics Signal Descriptions
Signal Name
Type
Description
G_FRAME#
G_IRDY#
G_TRDY#
G_STOP#
G_DEVSEL#
G_REQ#
G_GNT#
G_AD[31:0]
G_C/BE[3:0]#
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I/O
s/t/s
AGP
I
AGP
O
AGP
I/O
AGP
I/O
AGP
Not used during an AGP pipelined transaction.
G_FRAME# is an output from the GMCH-M during Fast Writes.
G_IRDY# indicates the AGP compliant master is ready to provide all write data
for the current transaction. Once IRDY# is asserted for a write operation, the
master is not allowed to insert wait states. The assertion of IRDY# for reads
indicates that the master is ready to transfer to a subsequent block (32 bytes) of
read data. The master is never allowed to insert a wait state during the initial
data transfer (32 bytes) of a read transaction. However, it may insert wait states
after each 32 byte block is transferred. (There is no G_FRAME# -- G_IRDY#
relationship for AGP transactions.)
For Fast Write transactions, G_IRDY# is driven by the GMCH-M to indicate
when the write data is valid on the bus. The GMCH-M deasserts this signal to
insert wait states on block boundaries.
G_TRDY# indicates the AGP compliant target is ready to provide read data for
the entire transaction (when the transfer size is less than or equal to 32 bytes)
or is ready to transfer the initial or subsequent block (32 bytes) of data when the
transfer size is greater than 32 bytes. The target is allowed to insert wait states
after each block (32 bytes) is transferred on both read and write transactions.
For Fast Write transactions the AGP master uses this signal to indicate if and
when it is willing to transfer a subsequent block.
G_STOP# Not used during an AGP transaction.
For Fast Write transactions G_STOP# is used to signal Disconnect or Target
Abort terminations.
G_DEVSEL# Not used during an AGP transaction.
For Fast Write transactions it is used when the transaction cannot complete
during the block.
G_REQ# (Used to request access to the bus to initiate a PCI or AGP request.)
G_GNT# Same meaning as PCI but additional information is provided on
ST[2:0]. The additional information indicates that the selected master is the
recipient of previously requested read data (high or normal priority), it is to
provide write data (high or normal priority), for a previously queued write
command or has been given permission to start a bus transaction (AGP or
PCI).
G_AD[31:0] Same as PCI.
G_C/BE[3:0]# Slightly different meaning. Provides command information
(different commands than PCI) when requests are being queued when using
PIPE#. Provide valid byte information during AGP write transactions and are not
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Datasheet
298338-001