82830MP Datasheet, PDF (73/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.27
Note:
ERRCMD - Error Command Register - Device #0
Address Offset:
Default Value:
Access:
Size:
94-95h
0000h
Read/Write
16 bits
This register enables various errors to generate an SERR Hub Interface special cycle. . Since the GMCH-
M does not have an SERR# signal, SERR messages are passed from the GMCH-M to the ICH3-M over
the Hub Interface. The actual generation of the SERR message is globally enabled for Device #0 via the
PCI Command register.
An error can generate one and only one Hub Interface error special cycle. The software is responsible to
ensure that when an SERR error message is enabled for an error condition, SMI and SCI error messages
are disabled for that same error condition.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
SERR on LOCK to non-SDRAM Memory. When this bit is set to “1”, the GMCH-M generates an SERR
Hub Interface special cycle when a CPU initiated LOCK transaction targeting non-SDRAM memory space
occurs. If this bit is “0” then reporting of this condition is disabled.
Default Value=0.
SERR on SDRAM Refresh timeout. When this bit is set to “1”, the GMCH-M generates an SERR Hub
Interface special cycle when a SDRAM Refresh timeout occurs. If this bit is “0” then reporting of this
condition is disabled.
Default Value=0.
SERR on SDRAM Throttle Condition. When this bit is set to “1”, the GMCH-M generates an SERR Hub
Interface special cycle when a SDRAM Read or Write Throttle condition occurs. If this bit is “0” then
reporting of this condition is disabled.
Default Value=0.
SERR on Receiving Target Abort on Hub Interface. When this bit is set to “1”, the GMCH-M generates
an SERR Hub Interface special cycle when a GMCH-M originated Hub Interface cycle is terminated with a
Target Abort. If this bit is “0” then reporting of this condition is disabled.
Default Value=0.
SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet. When this bit is
set to “1”, the GMCH-M generates an SERR Hub Interface special cycle when a GMCH-M initiated Hub
Interface request is terminated with a Unimplemented Special Cycle completion packet. If this bit is “0”
then reporting of this condition is disabled.
Default Value=0.
SERR on AGP Access Outside of Graphics Aperture. When this bit is set to “1”, the GMCH-M
generates an SERR Hub Interface special cycle when an AGP access occurs to an address outside of the
graphics aperture. If this bit is “0” then reporting of this condition is disabled.
Default Value=0.
SERR on Invalid AGP Access. When this bit is set to “1”, the GMCH-M generates an SERR Hub
Interface special cycle when an AGP access occurs to an address outside of the graphics aperture and
either to the 640K - 1M range or above the top of memory.
Default Value=0.
SERR on Access to Invalid Graphics Aperture Translation Table Entry. When this bit is set to “1”, the
GMCH-M generates an SERR Hub Interface special cycle when an invalid translation table entry was
returned in response to a AGP access to the graphics aperture. If this bit is “0” then reporting of this
condition via SERR messaging is disabled. Default Value=0.
Reserved
Reserved
298338-001
Datasheet
73