82830MP Datasheet, PDF (57/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
000 = 04
Default Value=111.
Recommended Value = 010 16
3:1
Reserved
0
MDA Present (MDAP) (R/W).
This bit works with the VGA Enable bit in the BCTRL register of device 1 to control the routing of CPU
initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be
set when the VGA Enable bit is not set. If the VGA enable bit is set, then accesses to IO address range
x3BCh-x3BFh are forwarded to Hub Interface. If the VGA enable bit is not set then accesses to IO address
range x3BCh-x3BFh are treated just like any other IO accesses i.e. the cycles are forwarded to AGP if the
address is within IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to Hub
Interface. MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFhI/O:
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in
decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded to Hub
Interface even if the reference includes I/O locations not listed above. The following table shows the
behavior for all combinations of MDA and VGA:
VGA MDA Behavior
Default 0
0 All References to MDA and VGA go to Hub Interface
0
1
Illegal Combination (DO NOT USE)
1
0
All References to VGA go to AGP/PCI.
MDA-only references (I/O address 3BF and aliases) will go to Hub Interface.
1
1
VGA References go to AGP/PCI; MDA References go to Hub Interface
Default Value=0.
298338-001
Datasheet
57