82830MP Datasheet, PDF (121/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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Line and Memory Read Multiple bursts. When the transaction terminates there may be a
minimum of 2 cache lines and a maximum of 2 cache line plus 7 Dwords buffered.
Subsequent Memory Reads hitting the buffers will return data from the buffer.
Memory Write and Memory Write and Invalidate - These commands are aliased and processed
identically. The GMCH-M supports data streaming for PCI-to-SDRAM writes based on its
ability to buffer up to 128 bytes (16 Qwords) of data before a snoop cycle must be completed
on the host bus. The GMCH-M is typically able to support longer write bursts, with the
maximum length dependent upon concurrent host bus traffic during PCI-SDRAM write data
streaming.
Fast Back-to-Back Transactions - GMCH-M as a target supports fast back-to-back cycles from a PCI
initiator.
As a PCI initiator the GMCH-M is responsible for translating host cycles to AGP/PCI1 cycles. The
GMCH-M also transfers hub interface to AGP/PCI1 write cycles. The following table shows all the
cycles that need to be translated.
Table 33. PCI Commands Supported by GMCH-M When Acting as an AGP/PCI1 Initiator
Source Bus
Command
Other Encoded Information
GMCH-M Host Bridge
Corresponding
PCI1 Command
C/BE[3:0]#
Encoding
Deferred Reply
Interrupt Acknowledge
Special Cycle
Branch Trace Message
I/O Read
I/O Write
I/O Read to 0CFCh
I/O Write to 0CFCh
Memory Read (Code or
Data)
Memory Read Invalidate
Source Bus: Host
Don’t Care
Length ≤ 8 Bytes
Shutdown
Halt
Stop Clock Grant
All other combinations
None
Length ≤ 8 Bytes up to 4 BEx
asserted
Length ≤ 8 Bytes up to 4 BEx
asserted
Length ≤ 8 Bytes up to 4 BEx
asserted
Length ≤ 8 Bytes up to 4 BEx
asserted
Length < 8 Bytes without all BEs
asserted
Length = 8 Bytes with all BEs
asserted
Length = 16 Bytes
Length = 32 Bytes Code Only
Length < 8 Bytes without all Bes
asserted
None
None
None
None
None
None
None
I/O Read
I/O Write
Configuration Read
Configuration Write
Memory Read
Memory Read
None
Memory Read
Memory Write
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0010
0011
1010
1011
0110
1110
N/A
1110
0111
298338-001
Datasheet
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