82830MP Datasheet, PDF (49/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.3
PCICMD - PCI Command Register - Device #0
Address Offset:
Default Value:
Access:
Size
04-05h
0006h
Read/Write
16 bits
Since GMCH-M Device #0 is the host-to-Hub Interface bridge, many of the PCI specific bits in this
register don’t apply.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back-to-Back. This bit controls whether or not the master can do fast back-to-back write. Since
device #0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit position
have no affect.
Default Value=0.
SERR Enable (SERRE). This bit is a global enable bit for Device #0 SERR messaging. The GMCH-M
does not have an SERR# signal. The GMCH-M communicates the SERR# condition by sending an SERR
message to the ICH. If this bit is set to a 1, the GMCH-M is enabled to generate SERR messages over
Hub Interface for specific Device #0 error conditions that are individually enabled in the ERRCMD register.
The error status is reported in the ERRSTS and PCISTS registers. If SERRE is reset to 0, then the SERR
message is not generated by the GMCH-M for Device #0.NOTE: This bit only controls SERR messaging
for the Device #0. Device #1 has its own SERRE bit to control error reporting for error conditions occurring
on Device #1. The two control bits are used in a logical OR manner to enable the SERR Hub Interface
message mechanism.
Default Value=0.
Address/Data Stepping. Address/data stepping is not implemented in the GMCH-M, and this bit is
hardwired to 0. Writes to this bit position have no effect.
Default Value=0.
Parity Error Enable (PERRE). PERR# is not implemented by the GMCH-M, and this bit is hardwired to 0.
Writes to this bit position have no effect.
Default Value=0.
VGA Palette Snoop. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this bit
position have no effect.
Default Value=0.
Memory Write and Invalidate Enable. The GMCH-M will never use this command and this bit is
hardwired to 0. Writes to this bit position have no effect.
Default Value=0.
Special Cycle Enable. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this
bit position have no effect.
Default Value=0.
Bus Master Enable (BME). The GMCH-M is always enabled as a master on Hub Interface. This bit is
hardwired to a 1. Writes to this bit position have no effect.
Default Value=1.
Memory Access Enable (MAE). The GMCH-M always allows access to main memory. This bit is not
implemented and is hardwired to 1. Writes to this bit position have no effect.
Default Value=1.
I/O Access Enable (IOAE). This bit is not implemented in the GMCH-M and is hardwired to a 0. Writes to
this bit position have no effect. Default Value=0.
298338-001
Datasheet
49