82830MP Datasheet, PDF (114/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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• Four Integrated Clock buffers
The 2-bank select lines SM_BA[1:0] and the 13 Address lines SM_MA[12:0] allow 830MP to support
64 bit wide SO-DIMMs using 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technology. While
address lines SM_MA[9:0] determine the starting address for a burst, burst lengths are fixed at 4. Six
chip selects SM_CS# lines allow maximum of three rows of single-sided SO-DIMMs and six rows of
double-sided SDRAM SO-DIMMs.
The Intel 830MP chipset’s main memory controller targets CAS latencies of 2 and 3 for SDRAM. The
830MP chipset provides refresh functionality with programmable rate (normal SDRAM rate is 1
refresh/15.6 ms). For write operations of less than a Qword in size, the Intel 830MP chipset will
perform a byte-wise write.
5.3.2 SDRAM Organization and Configuration
In the following discussion the term row refers to a set of memory devices that are simultaneously
selected by a SM_CS# signal. 830MP will support a maximum of 4 rows of memory. For the purposes
of this discussion, a “side” of a SO-DIMM is equivalent to a “row” of SDRAM devices.
The 2-bank select lines SM_BA[1:0] and the 13 Address lines SM_MA[12:0] allow 830MP to support
64-bit wide SO-DIMMs using x16 64 Mb, 128 Mb, 256 Mb, and 512 Mb SDRAM technologies.
Table 28. System Memory SO-DIMM Configurations
64 Mb
4M
X16
4
32 MB
12
8
128 Mb
8M
X16
4
64 MB
12
9
256 Mb
16M
X16
4
128 MB
13
9
512 Mb
32M
X16
4
256 MB
13
10
2
2 KB
128 MB
2
4 KB
256 MB
2
4 KB
512 MB
2
8 KB
1.0 GB
5.3.2.1
5.3.2.1.1
Configuration Mechanism for SO-DIMMs
Detection of the type of SDRAM installed on the SO-DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC SO-DIMM specification. This uses the SCL, SDA and SA[2:0]
pins on the SO-DIMMs to detect the type and size of the installed SO-DIMMs. No special
programmable modes are provided on the Intel 830MP chipset for detecting the size and type of memory
installed. Type and size detection must be done via the serial presence detection pins.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the Intel 830MPchipset SDRAM registers
must be initialized. The Intel 830MP chipset must be configured for operation with the installed
memory types. Detection of memory type and size is done via the System Management Bus (SMB)
interface on the ICH3-M. This two-wire bus is used to extract the SDRAM type and size information
from the serial presence detect port on the SDRAM SO-DIMMs. SDRAM SO-DIMMs contain a 5-pin
serial presence detect interface, including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on
the SMBus have a 7-bit address. For the SDRAM SO-DIMMs, the upper 4 bits are fixed at 1010. The
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Datasheet
298338-001