82830MP Datasheet, PDF (106/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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forces each memory address range to be aligned to 1-MB boundary and to have a size granularity of 1
MB.
The GMCH-M positively decodes memory accesses to AGP memory address space as defined by the
following equations:
Memory_Base_Address * Address * Memory_Limit_Address
Prefetchable_Memory_Base_Address * Address * Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The window size
depends on the size of memory claimed by the AGP device. Normally these ranges will reside above the
Top-of-Main-SDRAM and below High BIOS and APIC address ranges. They normally reside above the
top of memory (TOM) so they do not steal any physical SDRAM memory space.
It is essential to support a separate Prefetchable range in order to apply USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note that the GMCH-M Device #1 memory range registers described above are used to allocate memory
address space for any devices sitting on AGP that requires such a window. These devices would include
the AGP device, PCI-66 MHz/1.5V agents, and multifunctional AGP devices where one or more
functions are implemented as PCI devices.
The PCICMD1 register can override the routing of memory accesses to AGP. In other words, the
memory access enable bit must be set in the device 1, PCICMD1 register, to enable the memory
base/limit and prefetchable base/limit windows.
Host Interface
Overview
The GMCH-M is optimized for the Intel Pentium III Processor-M. The GMCH-M supports a PSB
frequency of 133 MHz using 1.25V AGTL+ signaling. The AGTL+ buffers support single-ended
termination. The GMCH-M supports 32-bit host addressing, decoding up to 4 GB of memory address
space for the processor. CPU memory writes to address space above 4 GB will be immediately
terminated and discarded. CPU memory reads to address space above 4 GB will be immediately
terminated and will return the value of the pulled-up GTL host bus. Host initiated I/O cycles are decoded
to AGP/PCI1, hub interface, or GMCH-M configuration space. Host initiated memory cycles are
decoded to AGP/PCI1, hub interface, or system SDRAM. Host cycles to AGP/PCI or hub interface, are
subject to dynamic deferring.
All memory accesses from the Host that hit the graphics aperture are translated using an AGP address
translation table. GMCH-M accesses to AGP/PCI1 device accesses to non-cacheable system memory are
not snooped on the host bus. Memory accesses initiated from AGP/PCI1 using PCI semantics,
cacheable accesses from hub interface to SDRAM will be snooped on the host bus.
Intel Pentium III Processor-M Unique PSB Activity
The GMCH-M recognizes and supports a large subset of the transaction types that are defined for the P6
bus interface. However, each of these transaction types has a multitude of response types, some of which
are not supported by this controller. All transactions are processed in the order that they are received on
the host bus. A summary of transactions supported by the GMCH-M is given in the following table.
Datasheet
298338-001