HD6475328CG Datasheet, PDF (94/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

External access cycle
Bus-right release cycle
CPU cycle
Ti *
Ti
Ti
Ti
TX*
TX
TX
T1
ø
A19 –A0
D7 –D0
RD, WR
R/W, DS
BREQ
BACK
(1)
(2)
(3)
(4)
(1) The BREQ pin is sampled at the start of a TI state and the Low level is detected.
(2) At the end of the internal operation cycle, the BACK pin goes Low and the CPU releases the bus.
(3) The BREQ pin is sampled at the TX state and a High level is detected.
(4) The BACK pin is returned to the High level, ending the bus-right release cycle.
Fig. 3-15
* TI : Internal CPU operation state.
TX : Bus-right released state.
Figure 3-15 Bus-Right Release Cycle (During Internal CPU Operation)
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