HD6475328CG Datasheet, PDF (121/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 5-2 Interrupts, Vectors, and Priorities
Interrupt
NMI
IRQ0
IRQ1
16-Bit ICI
FRT1 OCIA
OCIB
FOVI
16-Bit ICI
FRT2 OCIA
OCIB
FOVI
16-Bit ICI
FRT3 OCIA
OCIB
FOVI
8-Bit CMIA
timer CMIB
OVI
SCI ERI
RXI
TXI
A/D ADI
converter
Assignable
Priority
Levels
(Initial
Level)
8
(8)
7 to 0
(0)
7 to 0
(0)
7 to 0
(0)
IPR
Bits
—
IPRA
bits 6 to 4
IPRA
bits 2 to 0
IPRB
bits 6 to 4
7 to 0
(0)
IPRB
bits 2 to 0
7 to 0
(0)
IPRC
bits 6 to 4
7 to 0
(0)
7 to 0
(0)
7 to 0
(0)
IPRC
bits 2 to 0
IPRD
bits 6 to 4
IPRD
bits 2 to 0
Priority
within
Module
—
—
—
3
2
1
0
3
2
1
0
3
2
1
0
2
1
0
2
1
0
—
Vector Table
Entry Address
Minimum
Maximum
Mode
Mode
H'16 - H'17
H'2C - H'2F
Priority
among
Interrupts
on Same
Level*
High
H'40 - H'41
H'80 - H'83
H'42 - H'43
H'84 - H'87
H'48 - H'49
H'4A - H'4B
H'4C - H'4D
H'4E - H'4F
H'50 - H'51
H'52 - H'53
H'54 - H'55
H'56 - H'57
H'58 - H'59
H'5A - H'5B
H'5C - H'5D
H'5E - H'5F
H'60 - H'61
H'62 - H'63
H'64 - H'65
H'68 - H'69
H'6A - H'6B
H'6C - H'6D
H'70 - H'71
H'90 - H'93
H'94 - H'97
H'98 - H'9B
H'9C - H'9F
H'A0 - H'A3
H'A4 - H'A7
H'A8 - H'AB
H'AC - H'AF
H'B0 - H'B3
H'B4 - H'B7
H'B8 - H'BB
H'BC - H'BF
H'C0 - H'C3
H'C4 - H'C7
H'C8 - H'CB
H'D0 - H'D3
H'D4 - H'D7
H'D8 - H'DB
H'E0 - H'E3
Low
* If two or more interrupts are requested simultaneously, they are handled in order of priority level,
as set in registers IPRA to IPRD. If they have the same priority level because they are requested
from the same on-chip supporting module, they are handled in a fixed priority order within the
module. If they are requested from different modules to which the same priority level is
assigned, they are handled in the order indicated in the right-hand column.
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