HD6475328CG Datasheet, PDF (383/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

P1CR—Port 1 Control Register
H'FFFC
Port 1
Bit
7
6
5
4
3
2
1
0
—
IRQ1E IRQ0E NMIEG BRLE
—
—
—
Initial value
1
0
0
0
0
1
1
1
Read/Write
—
R/W R/W R/W R/W
—
—
—
Bus Release Enable
0 P12 and P13 are I/O ports.
1 P12 is the output pin and
P13 is the input pin.
Nonmaskable Interrupt Edge
0 An NMI request is generated on the
falling edge of the NMI pin input.
1 An NMI request is generated on the
rising edge of the NMI pin input.
Interrupt Request 0 Enable
0 P15 is an I/O port; input is disabled.
1 P15 is the input pin.
Interrupt Request 1 Enable
0 P16 is an I/O port; input is disabled.
1 P16 is the input pin.
P2DDR—Port 2 Data Direction Register
H'FF81
Port 2
Bit
7
6
5
4
3
2
1
0
—
—
— P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
W
W
W
W
W
Port 2 Input/Output Selection
0 Input port
1 Output port
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