HD6475328CG Datasheet, PDF (130/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

5.6 Interrupt Response Time
Table 5-4 indicates the number of states that may elapse between the generation of an interrupt
request and the execution of the first instruction of the interrupt-handling routine, assuming that
the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is
performed to on-chip memory areas, fastest interrupt service can be obtained by placing the
program in on-chip ROM and the stack in on-chip RAM.
Table 5-4 Number of States before Interrupt Service
No. Reason for Wait
1 Interrupt priority decision and comparison with
mask level in CPU status register
2 Maximum number of Instruction is in on-chip
states to completion memory
of current instruction
Instruction is in external
memory
3 Saving of PC and SR Stack is in on-chip RAM
or PC, CP, and SR
Stack is in external memory
and instruction prefetch
Stack is in
Instruction is in on-chip
on-chip RAM
memory
Instruction is in external
Total
memory
Stack is in
Instruction is in on-chip
external RAM
memory
Instruction is in external
memory
Number of States
Minimum Mode Maximum Mode
2 states
x
(x = 38 for LDM instruction specifying
all registers)
y
(y = 74 + 16m for LDM instruction
specifying all registers)
16
21
28 + 6m
41 + 10m
18 + x
(56)
18 + y
(92 + 16m)
30 + 6m + x
(68 + 6m)
30 + 6m + y
(104 + 22m)
23 + x
(61)
23 + y
(97 + 16m)
43 + 10m + x
(81 + 10m)
43 + 10m + y
(117 + 26m)
Note: m: Number of wait states inserted in external memory access.
Values in parentheses are for the LDM instruction.
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