HD6475328CG Datasheet, PDF (294/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

< Upper byte read >
CPU
receives
data H’AA
Bus interface
Module data bus
TEMP
[H’40]
ADDRn H
[H’AA]
ADDRn L
[H’40]
(n = A to D)
< Lower byte read >
CPU
receives
data H’40
Bus interface
Module data bus
TEMP
[H’40]
ADDRn H
[H’AA]
ADDRn L
[H’40]
(n = A to D)
Figure 15-2 Read Access to A/D Data Register (When Register Contains H'AA40)
15.4 Operation
The A/D converter performs 10 successive approximations to obtain a result ranging from H'0000
(corresponding to AVSS) to H'FFC0 (corresponding to AVCC). Only the first 10 bits of the result
are significant.
The A/D converter module can be programmed to operate in single mode or scan mode as
explained below.
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