HD6475328CG Datasheet, PDF (449/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

3. Mode 3
Figures E-5 and E-6 show how the pin states change when the RES pin goes Low during external
memory access in mode 3.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D7 to D0) is placed in the high-impedance
state.
The address bus and the signal are initialized 1.5 ø clock periods after the Low state of the RES
pin is sampled. All address bus signals are made Low. The R/W signal is made High.
The clock output pins P10/ø and P11/E are initialized 0.5 ø clock periods after the Low state of the
RES pin is sampled. Both pins are initialized to the output state.
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