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HD6475328CG Datasheet, PDF (56/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description | |||
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Bits 7 to 4âReserved: These bits cannot be modified and are always read as â0.â
Bit 3âNegative (N): This bit indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2âZero (Z): This bit is set to â1â to indicate a zero result and cleared to â0â to indicate a
nonzero result.
Bit 1âOverflow (V): This bit is set to â1â when an arithmetic overflow occurs, and cleared to
â0â at other times.
Bit 0âCarry (C): This bit is set to â1â when a carry or borrow occurs at the most significant bit,
and is cleared to â0â (or left unchanged) at other times.
The specific changes that occur in the condition code bits when each instruction is executed are
listed in appendix A.1 âInstruction Tables.â See the H8/500 Series Programming Manual for
further details.
Page Registers: The code page register (CP), data page register (DP), extended page register
(EP), and stack page register (TP) are 8-bit registers that are used only in the maximum mode. No
use of their contents is made in the minimum mode.
In the maximum mode, the page registers combine with the program counter and general registers
to generate 24-bit effective addresses as shown in figure 3-4, thereby expanding the program area,
data area, and stack area.
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