HD6475328CG Datasheet, PDF (114/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 4-3 Stack after Exception Handling Sequence (cont)
Exception Factor
Minimum Mode
Maximum Mode
Invalid
instruction ^SP
SR (upper byte)
SR (lower byte)
PC when error occurred (upper byte)
PC when error occurred (lower byte)
TP:SP
SR (upper byte)
SR (lower byte)
Don’t-care
CP when error occurred (8 bits)
PC when error occurred (upper byte)
PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is not necessarily the address of the first
byte of the invalid instruction.
Address
error
SP
SR (upper byte)
TP:SP
SR (upper byte)
SR (lower byte)
PC when error occurred (upper byte)
SR (lower byte)
Don’t-care
PC when error occurred (lower byte)
CP when error occurred (8 bits)
PC when error occurred (upper byte)
PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is the address of the next instruction after
the last instruction successfully executed.
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