HD6475328CG Datasheet, PDF (319/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

18.2 Sleep Mode
18.2.1 Transition to Sleep Mode
Execution of the SLEEP instruction causes a transition from the program execution state to the
sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal
registers remain unchanged. The functions of the on-chip supporting modules do not stop in the
sleep mode.
18.2.2 Exit from Sleep Mode
The chip wakes up from the sleep mode when it receives an internal or external interrupt request,
or a Low input at the RES or STBY pin.
1. Wake-Up by Interrupt: An interrupt releases the sleep mode and starts either the CPU’s
interrupt-handling sequence or the data transfer controller (DTC).
If the interrupt is served by the DTC, after the data transfer is completed the CPU executes the
instruction following the SLEEP instruction, unless the count in the data transfer count register
(DTCR) is 0.
If an interrupt on a level equal to or less than the mask level in the CPU’s status register (SR) is
requested, the interrupt is left pending and the sleep mode continues. Also, if an interrupt from
an on-chip supporting module is disabled by the corresponding enable/disable bit in the
module’s control register, the interrupt cannot be requested, so it cannot wake the chip up.
2. Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to the
reset state.
3. Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode to
the hardware standby mode.
18.3 Software Standby Mode
18.3.1 Transition to Software Standby Mode
A program enters the software standby mode by setting the standby bit (SSBY) in the software
standby control register (SBYCR) to 1, then executing the SLEEP instruction. Table 18-2 lists the
attributes of the software standby control register.
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