HD6475328CG Datasheet, PDF (260/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Section 14 Serial Communication Interface
14.1 Overview
The H8/532 chip includes a single-channel serial communication interface (SCI) for transferring
serial data to and from other chips. The SCI supports both synchronous and asynchronous data
transfer. Communication control functions are provided by eight internal registers.
14.1.1 Features
The features of the on-chip serial communication interface are:
• Selection of asynchronous or synchronous mode
— Asynchronous mode
The SCI can communicate with a UART (Universal Asynchronous Receiver/Transmitter),
ACIA (Asynchronous Communication Interface Adapter), or other chip that employs
standard asynchronous serial communication. Eight data formats are available.
— Data length: 7 or 8 bits
— Stop bit length: 1 or 2 bits
— Parity: Even, odd, or none
— Error detection: Parity, overrun, and framing errors
— Synchronous mode
The SCI can communicate with chips able to synchronize data transfers with clock pulses.
— Data length: 8 bits
— Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. Both the transmit and receive sections use double buffering, so continuous data
transfer is possible in either direction.
• Built-in baud rate generator
Any specified bit rate can be generated.
• Internal or external clock source
The baud rate generator can operate on an internal clock source, or an external clock signal
input at the SCK pin.
• Three interrupts
Transmit-end, receive-end, and receive-error interrupts are requested independently. The
transmit-end and receive-end interrupts can be served by the on-chip data transfer controller
(DTC), providing a convenient way to transfer data with minimal CPU programming.
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