HD6475328CG Datasheet, PDF (200/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system
clock periods (1.5·ø).
ø
FTI
Minimum FTI Pulse Width
The ICR is initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the ICR even if the input
capture flag (ICF) is already set.
10.2.4 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
6
5
4
ICIE OCIEB OCIEA OVIE
0
0
0
0
R/W R/W R/W R/W
3
OEB
0
R/W
2
OEA
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
The TCR is an 8-bit readable/writable register that selects the FRC clock source, enables the
output compare signals, and enables interrupts.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Capture Interrupt Enable (ICIE): This bit selects whether to request an input
capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register
(TCSR) is set to “1.”
Bit 7
ICIE
0
1
Description
The input capture interrupt request (ICI) is disabled.
The input capture interrupt request (ICI) is enabled.
(Initial value)
Bit 6—Output Compare Interrupt Enable B (OCIEB): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer
status/control register (TCSR) is set to “1.”
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