HD6475328CG Datasheet, PDF (55/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 3-1 Interrupt Mask Levels
Priority
High
Low
Mask
Level
7
6
5
4
3
2
1
0
Mask Bits
I2 I1 I0
111
110
101
100
011
010
001
000
Interrupts Accepted
NMI
Level 7 and NMI
Levels 6 to 7 and NMI
Levels 5 to 7 and NMI
Levels 4 to 7 and NMI
Levels 3 to 7 and NMI
Levels 2 to 7 and NMI
Levels 1 to 7 and NMI
Table 3-2 Interrupt Mask Bits after an Interrupt is Accepted
Level of Interrupt Accepted
NMI (8)
7
6
5
4
3
2
1
I2
I1
I0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
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