HD6475328CG Datasheet, PDF (445/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Masked-ROM Versions
P10 / ø*
RES
Internal reset signal
A15 to A0
External memory access
T1
T2
T3
H’0000
R/W
AS, RD and DS (read)
WR and DS (write)
D7 to D0 (write)
I/O ports
High impedance
High impedance
* _{The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,}
but a clock output pin if the DDR bit is 1.
Figure E-2 Reset during Memory Access (Mode 1)
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