HD6475328CG Datasheet, PDF (249/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

12.4 Application Notes
Two notes on the use of the PWM timer module are given below.
1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to 1.
2. If the DTR value is H'00, the duty factor is 0% and PWM output remains constant at 0. If the
DTR value is H'FA to H'FF, the duty factor is 100% and PWM output remains constant at 1.
(For positive logic, 0 is Low and 1 is High. For negative logic, 0 is High and 1 is Low.)
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