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HD6475328CG Datasheet, PDF (347/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description | |||
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Size CCR Bit
Mnemonic
Operation
B/W N Z V C
Data MOV: G (EAs) â Rd
B/W ¤ ¤ 0 â
transfer
Rs â (EAd)
#IMM â (EAd)
MOV: E #IMM â Rd
(short format)
MOV: F @ (d: 8, FP) â Rd
B ¤ ¤0â
B/W ¤ ¤ 0 â
MOV: I
Rs â @ (d: 8, FP)(short format)
#IMM â Rd
(short format)
W ¤ ¤0â
MOV: L (@aa: 8) â Rd (short format)
MOV: S Rs â (@aa: 8) (short format)
B/W ¤ ¤ 0 â
B/W ¤ ¤ 0 â
LDM
@ SP + â Rn (register list)
W â âââ
STM
Rn (register list) â @ â SP
W â âââ
XCH
SWAP
Rs ââ Rd
Rd (upper byte) ââ Rd (lower byte)
W â âââ
B ¤ ¤0â
MOVTPE Rs â (EAd) Synchronized with E clock B â â â â
MOVFPE (EAs) â Rd Synchronized with E clock B â â â â
Arith- ADD: G Rd + (EAs) â Rd
metic ADD: Q (EAd) + #IMM â (EAd)
B/W ¤ ¤ ¤ ¤
B/W ¤ ¤ ¤ ¤
opera-
(#IMM = ±1, ±2)
(short format)
tions ADDS Rd + (EAs) â Rd
B/W â â â â
(Rd is always word size)
ADDX Rd + (EAs) + C â Rd
B/W ¤ ¤ ¤ ¤
DADD
SUB
(Rd)10 + (Rs)10 + C â (Rd)10
Rd â (EAs) â Rd
B â ¤ â¤
B/W ¤ ¤ ¤ ¤
SUBS
SUBX
Rd â (EAs) â Rd
Rd â (EAs) â C â Rd
B/W â â â â
B/W ¤ ¤ ¤ ¤
DSUB
(Rd)10 â (Rs)10 â C â (Rd)10
MULXU Rd à (EAs) â Rd 8 à 8
B â ¤ â¤
B/W ¤ ¤ 0 0
DIVXU
(Unsigned)
16 Ã 16
Rd ÷ (EAs) â Rd 16 ÷ 8
B/W ¤ ¤ ¤ 0
(Unsigned)
32 ÷ 16
CMP: G Rd â (EAs), Set CCR
B/W ¤ ¤ ¤ ¤
(EAd) â #IMM, Set CCR
CMP: E Rd â #IMM, Set CCR (short format)
B ¤ ¤¤¤
CMP: I Rd â #IMM, Set CCR (short format)
W ¤ ¤¤¤
338
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