HD6475328CG Datasheet, PDF (109/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Access to Disabled RAM Area: The on-chip RAM area (H'FB80 to H'FF7F) can be disabled by
clearing the RAME bit in the RAM control register (RAMCR). If RAM access is attempted in
this state in the single-chip mode, an address error occurs.
4.4 Trace
When the T bit of the status register is set to “1,” the CPU operates in trace mode. A trace
exception occurs at the completion of each instruction. The trace mode can be used to execute a
program for debugging by a debugger.
In the trace exception sequence the T bit of the status register is cleared to “0” to disable the trace
mode while the trace routine is executing. The interrupt mask level in bits I2 to I0 is not changed.
Interrupts are accepted as usual during the trace routine.
In the status-register data saved on the stack, the T bit is set to “1.” When the trace routine returns
with the RTE instruction, the status register is popped from the stack and the trace mode resumes.
If an address error occurs during execution of the first instruction after the return from the trace
routine, since the address error has higher priority, the address error exception-handling sequence
is initiated, clearing the T bit in the status register to “0” and making it impossible to trace this
instruction.
4.5 Interrupts
Interrupts can be requested from three external sources (NMI, IRQ0, and IRQ1) and seven on-chip
supporting modules: the 16-bit free-running timers (FRT1 to FRT3), the 8-bit timer, the serial
communication interface (SCI), the A/D converter, and the watchdog timer (WDT). The on-chip
interrupt sources can request a total of nineteen different types of interrupts, each having its own
interrupt vector. Figure 4-5 lists the interrupt sources and the number of different interrupts from
each source.
Each interrupt source has a priority. NMI interrupts have the highest priority, and are normally
accepted unconditionally. The priorities of the other interrupt sources are set in control registers
(IPR A to D) in the register field at the high end of page 0 and can be changed by software.
Priority levels range from 0 (low) to 7 (high), with NMI considered to be on level 8.
The on-chip interrupt controller decides whether an interrupt can be accepted by comparing its
priority with the interrupt mask level, and determines the order in which to accept competing
interrupt requests. Interrupts that are not accepted immediately remain pending until they can be
accepted later.
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