HD6475328CG Datasheet, PDF (211/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Read cycle: CPU reads upper byte of ICR
T1
T2
T3
ø
Input at FTI pin
Internal input
capture signal
Figure 10-8 Input Capture Timing (1-State Delay)
Timing of Input Capture Flag (ICF) Setting: The input capture flag (ICF) is set to “1” by the
internal input capture signal. Figure 10-9 shows the timing of this operation.
ø
Internal input
capture signal
ICF
FRC
ICR
N–1
N
N+1
N
Figure 10-9 Setting of Input Capture Flag
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