HD6475328CG Datasheet, PDF (122/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

5.3 Register Descriptions
5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD)
IRQ0, IRQ1, and the on-chip supporting modules are each assigned three bits in one of the four
interrupt priority registers (IPRA to IPRD). These bits specify a priority level from 7 (high) to 0
(low) for interrupts from the corresponding source. The drawing below shows the configuration
of the interrupt priority registers. Table 5-3 lists their assignments to interrupt sources.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
0
0
0
0
0
0
0
0
R
R/W R/W R/W
R
R/W R/W R/W
Note: Bits 7 and 3 are reserved. They cannot be modified and are always read as “0.”
Table 5-3 Assignment of Interrupt Priority Registers
Register
IPRA
IPRB
IPRC
IPRD
Interrupt Request Source
Bits 6 to 4 Bits 2 to 0
IRQ0
IRQ1
16-Bit FRT1 16-Bit FRT2
16-Bit FRT3 8-Bit timer
SCI
A/D converter
Address
H'FFF0
H'FFF1
H'FFF2
H'FFF3
As table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt
sources. A user program can assign desired levels to these interrupt sources by writing “000” in
bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or “111” to set priority level 7.
A reset clears registers IPRA to IPRD to H'00, so all interrupts except NMI are initially masked.
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