HD6475328CG Datasheet, PDF (457/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Appendix F Timing of Entry to and Recovery from
Hardware Standby Mode
Timing of Entry to Hardware Standby Mode
(1) To preserve RAM contents, drive the RES signal line low 10 system clock cycles before the
fall of the STBY signal.
The RES signal can rise any time after STBY goes low. The minimum necessary time from
STBY low to RES high is 0 ns.
STBY
RES
t1
t2
(2) When it is not necessary to preserve RAM contents, RES need not be driven low as in (1).
Timing of Exit from Hardware Standby Mode
Drive the RES signal line low approximately 100 ns before the rise of the STBY signal.
STBY
RES
t = 100ns
tOSC
449