HD6475328CG Datasheet, PDF (451/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Masked-ROM Version
P10 / ø*
External memory access
T1
T2
RES
Internal reset signal
A19 to A0
H’0000
R/W
AS, RD and DS (read)
WR and DS (write)
D7 to D0 (write)
High impedance
I/O ports
High impedance
* _{The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,}
but a clock output pin if the DDR bit is 1.
Figure E-6 Reset during Memory Access (Mode 3)
442