HD6475328CG Datasheet, PDF (90/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

BREQ = “1”
BREQ = “0”
Program execution state
BREQ = “0”
BREQ = “1”
End of
exception
Bus-released state
handling
Request
for exception
handling
SLEEP
SLEEP _instruction
instruction
with standby
flag set
Sleep mode
Interrupt request
Exception-handling
NMI
Software standby mode
state
Reset state ^{* 1}
STBY = “1”, RES = “0”
Hardware standby mode^{* 2}
*1 From any state except the hardware standby mode, a transition to the reset state occurs
whenever RES goes Low.
*2 A transition to the hardware standby mode from any state occurs when STBY goes Low.
Figure 3-12 State Transitions
3.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
3.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to an interrupt, trap instruction, address error, or other exception. In this state
the CPU carries out a hardware-controlled sequence that prepares it to execute a user-coded
exception-handling routine.
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