HD6475328CG Datasheet, PDF (125/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Program execution state
Address
error?
Y
N
Interrupt requested?
Y
N
N
Trace?
N
NMI?
N
Y
Y
Level-7 interrupt?
Y
N
Level-6 interrupt?
Level-1 interrupt? ^N
Y
Y
Mask level
Mask level
Mask level
in SR ≤ 6?
N
in SR ≤ 5?
N
in SR = 0?
N
Y
Y
Y
Exception-handling
sequence
Data transfer
enabled?
N
Interrupt remains pending
Y
Start DTC
Read DTC vector
Read transfer mode
Save PC
Read source address
Maximum
mode?
N
Y
Save PC
Save SR
Read data
Source
Y
address increment
mode?
N
Increment source
address (+1 or +2)
Write source address
Clear T bit
N
Trace
Address
N
error?
Y
Update mask level
Read destination address
Write data
Destination
Y
address increment
mode?
N
Increment source
address (+1 or +2)
Write destination
address
Vectoring
To user-coded
exception-handling
routine
Read DTCR
DTCR-1 → DTCR
Write DTCR
Y
DTCR = 0?
N
Figure 5-2 Interrupt Handling Flowchart
106