HD6475328CG Datasheet, PDF (201/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Bit 6
OCIEB
0
1
Description
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 5—Output Compare Interrupt Enable A (OCIEA): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer
status/control register (TCSR) is set to “1.”
Bit 5
OCIEA
0
1
Description
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 4—Timer overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer
status/control register (TCSR) is set to “1.”
Bit 4
OVIE
0
1
Description
The free-running timer overflow interrupt request (FOVI) is disabled.
The free-running timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 3—Output Enable B (OEB): This bit selects whether to enable or disable output of the logic
level selected by the OLVLB bit in the timer status/control register (TCSR) at the output compare
B pin when the FRC and OCRB values match.
Bit 3
OEB
0
1
Description
Output compare B output is disabled.
Output compare B output is enabled.
(Initial value)
Bit 2—Output Enable A (OEA): This bit selects whether to enable or disable output of the logic
level selected by the OLVLA bit in the timer status/control register (TCSR) at the output compare
A pin when the FRC and OCRA values match.
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