HD6475328CG Datasheet, PDF (33/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A)
Expanded Minimum
Pin
Modes
No.
Mode 1
Mode 2
1
R/W
R/W
2
DS
DS
3
RD
RD
4
WR
WR
5
VCC
VCC
6
MD0
MD0
7
MD1
MD1
8
MD2
MD2
9
STBY
STBY
10
RES
RES
11
NMI
NMI
12
VSS
VSS
13
D0
D0
14
D1
D1
15
D2
D2
16
D3
D3
17
D4
D4
18
D5
D5
19
D6
D6
20
D7
D7
21
A0
A0
Pin Name
Expanded Maximum
Modes
Mode 3
Mode 4
R/W
R/W
DS
DS
RD
RD
WR
WR
VCC
VCC
MD0
MD0
MD1
MD1
MD2
MD2
STBY
STBY
RES
RES
NMI
NMI
VSS
VSS
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
A0
A0
Single-Chip
Mode
Mode 7
P21
P22
P23
P24
VCC
MD0
MD1
MD2
STBY
RES
NMI
VSS
P30
P31
P32
P33
P34
P35
P36
P37
P40
PROM
Mode
NC
NC
NC
NC
VCC
VSS
VSS
VSS
VSS
VPP
A9
VSS
O0
O1
O2
O3
O4
O5
O6
O7
A0
Notes: 1. For the PROM mode, see section 17, “ROM.”
2. Pins marked NC should be left unconnected.
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