HD6475328CG Datasheet, PDF (237/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Contention between TCNT Write and Increment: If a timer counter increment pulse is
generated during the T3 state of a write cycle to the timer counter, the write takes priority and the
timer counter is not incremented.
Figure 11-10 shows this type of contention.
Write cycle: CPU writes to TCNT
T1
T2
T3
ø
Internal Address
bus
Internal write
signal
TCNT clock
pulse
TCNT address
TCNT
N
M
Write data
Figure 11-10 TCNT Write-Increment Contention
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