HD6475328CG Datasheet, PDF (110/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

When it accepts an interrupt, the interrupt controller also decides whether to interrupt the CPU or
start the on-chip data transfer controller (DTC). This decision is controlled by bits set in four data
transfer enable registers (DTE A to D) in the register field. The DTC is started if the corresponding
DTE bit is set to “1;” otherwise a CPU interrupt is generated. DTC interrupts provide an efficient
way to send and receive blocks of data via the serial communication interface, or to transfer data
between memory and I/O without detailed CPU programming. The CPU stops while the DTC is
operating. DTC interrupts are described in section 6, “Data Transfer Controller.”
The hardware exception-handling sequence for a CPU interrupt clears the T bit in the status
register to “0” and sets the interrupt mask level in bits I2 to I0 to the level of the interrupt it has
accepted. This prevents the interrupt-handling routine from being interrupted except by a higher-
level interrupt. The previous interrupt mask level is restored on the return from the interrupt-
handling routine.
For further information on interrupts, see section 5, “Interrupt Controller.”
External
interrupts
NMI (1)
IRQ0 (1)
IRQ1 (1)
Interrupt
sources
Internal
interrupts
NMI:
IRQ:
FRT:
SCI:
WDT:
NonMaskable Interrupt
Interrupt Request
Free-Running Timer
Serial Communication Interface
WatchDog Timer
16-Bit FRT1 (4)
16-Bit FRT2 (4)
16-Bit FRT3 (4)
8-Bit timer (3)
SCI (3)
A/D converter (1)
WDT^*
* Interrupts from the watchdog timer are handled as NMI or IRQ0.
Figure 4-5 Interrupt Sources (and Number of Interrupt Types)
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