HD6475328CG Datasheet, PDF (441/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table E-1 Port State (cont)
Port
Pin Name
P63 to P60
A19 to A16
P77 to P70
P87 to P80
P97 to P90
Mode Reset
1
2T
3L
4T
7
1
2
3T
4
7
1
2
3T
4
7
1
2
3T
4
7
Hardware
Standby Software
Mode
Standby mode Sleep Mode
keep
keep
T
T
L
T^*6
*5
keep
keep
T
keep^*2
keep
T
T
T
T
keep^*2
keep
Bus-right
Program Execution
Release Mode State (Normal Operation)
keep
Input/Output port
T
A19 to A16
T^*6
Address/Input port
---
Input/Output port
keep
Input port
T
Input port
keep
Input/Output port
H: “High” = High level
L: “Low” = Low level
T: High Impedance
keep: If DDR = 0 and DR = 1 in port 5 and 6, Pull-up MOS holds on-state.
Notes:
*1 8 Bit Timer is reset, so P17 becomes input or output port controlled by DDR and DR. Also P12
goes to the high impedance state when it is programmed as BACK output.
*2 On-chip supporting modules are reset. So these pins become input or output ports controlled
by DDR and DR.
*3 BREQ can be accepted and BACK goes LOW.
*4 BACK outputs LOW.
*5 The pins programmed as address bus output LOW and others programmed as input are at the
high impedance state.
If DDR = 0 and DR = 1, the pull-up MOS’s keep ON state.
*6 If DDR = 0 and DR = 1, the pull-up MOS’s keep ON state.
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