HD6475328CG Datasheet, PDF (270/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

14.2.8 Bit Rate Register (BRR)—H'FFD9
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the bit rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 14-3 and 14-4 show examples of BRR (N) and CKS (n) settings for commonly used bit
rates.
Table 14-3 Examples of BRR Settings in Asynchronous Mode (1)
Bit
Rate n
110 1
150 0
300 0
600 0
1200 0
2400 0
4800 —
9600 —
19200 —
31250 —
38400 —
2
N
70
207
103
51
25
12
—
—
—
—
—
Error
(%)
+0.03
+0.16
+0.16
+0.16
+0.16
+0.16
—
—
—
—
—
XTAL Frequency (MHz)
2.4576
4
Error
Error
n N (%) n N (%)
1 86 +0.31 1 141 +0.03
0 255 0
1 103 +0.16
0 127 0
0 207 +0.16
0 63 0
0 103 +0.16
0 31 0
0 51 +0.16
0 15 0
0 25 +0.16
07
0
0 12 +0.16
03
0
—— —
01
0
—— —
—— —
01 0
00
0
—— —
4.194304
Error
n N (%)
1 148 –0.04
1 108 +0.21
0 217 +0.21
0 108 +0.21
0 54 –0.70
0 26 +1.14
0 13 –2.48
—— —
—— —
—— —
—— —
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