HD6475328CG Datasheet, PDF (456/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Masked-ROM Versions
P10 / ø*
P10 /E*
RES
Internal reset signal
I/O ports
High impedance
* _{The dotted line indicates that P10/ø and P10/E are input port if the corresponding DDR}
bit is 0, but clock output pins if the DDR bit is 1.
Figure E-10 Reset during Memory Access (Mode 7)
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