HD6475328CG Datasheet, PDF (180/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

A: Before Execution of BSET Instruction
MOV.B #80, R0
MOV.B R0, @RAM0
MOV.B R0, @PORT5
;write data (H'80) for data register
;write to work area (RAM0)
;write to P5DR
Input/output
Pin state
DDR
DR
Pull-up
RAM0
P5₇
Input
Low
0
1
On
1
P5₆
Input
High
0
0
Off
0
P5₅
Output
Low
1
0
Off
0
P5₄
Output
Low
1
0
Off
0
P5₃
Output
Low
1
0
Off
0
P5₂
Output
Low
1
0
Off
0
P5₁
Output
Low
1
0
Off
0
P5₀
Output
Low
1
0
Off
0
B: Execution of BSET Instruction
BSET.B #0, @RAM0
;set bit 0 in work area (RAM0)
C: After Execution of BSET Instruction
MOV.B @RAM0, R0
MOV.B R0, @PORT5
;get value in work area (RAM0)
;write value to P5DR
Input/output
Pin state
DDR
DR
Pull-up
RAM0
P5₇
Input
Low
0
1
On
1
P5₆
Input
High
0
0
Off
0
P5₅
Output
Low
1
0
Off
0
P5₄
Output
Low
1
0
Off
0
P5₃
Output
Low
1
0
Off
0
P5₂
Output
Low
1
0
Off
0
P5₁
Output
Low
1
0
Off
0
P5₀
Output
High
1
1
Off
0
9.7 Port 6
9.7.1 Overview
Port 6 is a 4-bit input/output port with the pin configuration shown in figure 9-15. In mode 4 (the
expanded maximum mode that uses the on-chip ROM), the pins of port 6 function either as
general-purpose input pins or as the page address bus, depending on the port 6 data direction
register (P6DDR).
Port 6 has built-in MOS pull-ups that can be turned on or off under program control.
Outputs from port 6 can drive one TTL load and a 90pF capacitive load. They can also drive a
Darlington transistor pair.
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