HD6475328CG Datasheet, PDF (215/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Example c: ø/32 clock source, 32-state write interval (n = 1), on-chip memory
LC: LDC.B #H'FF,BR
LDC.W #H'0700,SR
MOV.W #m,R1
MOV.W #m+1,R2
MOV.W #m+2,R3
BSR SET32
.ALIGN 2
SET32: MOV:S.W R1,@H'92:8
BSR WAIT:8
MOV:S.W R2,@H'A2:8
BSR WAIT:8
MOV:S.W R3,@H'B2:8
RTS
; Align on even address
; 2 Bytes, 9 states
; 2 Bytes, 9 states
Total 32 states
WAIT:
.ALIGN 2
NOP
XCH R1,R1
RTS
; Align on even address
; 2 States
; 4 States
; 8 States
Note: The stack is assumed to be in on-chip RAM.
Example d: ø/4 clock source, 20-state write interval (n = 5), external memory
LD: LDC.B #H'FF,BR
LDC.W #H'0700,SR
; Set interrupt mask level to 7
CLR.B @H'F8:8
; Disable wait states
MOV.W #m,R1
MOV.W #m+5,R2
MOV.W #m+10,R3
MOV:S.W R1,@H'92:8
BRN LD:8
; 13 States
; 2 Bytes, 7 states
Total 20 states
MOV:S.W R2,@H'A2:8
BRN LD:8
MOV:S.W R3,@H'B2:8
198