HD6475328CG Datasheet, PDF (264/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

14.2.5 Serial Mode Register (SMR)—H'FFD8
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP
—
CKS1 CKS0
Initial value
0
0
0
0
0
1
0
0
Read/Write
R/W R/W R/W R/W R/W
—
R/W R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby
modes.
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
0
1
Description
Asynchronous communication.
(Initial value)
Communication is synchronized with the serial clock.
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR
0
1
Description
8 Bits per character.
7 Bits per character.
(Initial value)
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE
0
1
Description
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is not checked.
(Initial value)
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