HD6475328CG Datasheet, PDF (239/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Table 11-4 Priority Order of Timer Output
Output Selection
Toggle
“1” Output
“0” Output
No change
Priority
High
Low
Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the timer counter to increment. This depends on the
time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in table 11-5.
The pulse that increments the timer counter is generated at the falling edge of the internal clock
source signal. If clock sources are changed when the old source is High and the new source is
Low, as in case No. 3 in table 11-5, the changeover generates a falling edge that triggers the
TCNT clock pulse and increments the timer counter.
Switching between an internal and external clock source can also cause the timer counter to
increment.
Table 11-5 Effect of Changing Internal Clock Sources
No. Description
1 Low → Low^*1:
CKS1 and CKS0 are
rewritten while both
clock sources are Low.
Timing Chart
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
N
CKS rewrite
N+1
Note: *1 Including a transition from Low to the stopped state (CKS1 = 0, CKS0 = 0), or a
transition from the stopped state to Low.
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