HD6475328CG Datasheet, PDF (204/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Bit 3
OLVLB
0
1
Description
A “0” logic level (Low) is output for compare-match B.
A “1” logic level (High) is output for compare-match B.
(Initial value)
Bit 2—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 2
OLVLA
0
1
Description
A “0” logic level (Low) is output for compare-match A.
A “1” logic level (High) is output for compare-match A.
(Initial value)
Bit 1—Input Edge Select (IEDG): This bit selects whether to capture the count on the rising or
falling edge of the input capture signal.
Bit 1
IEDG
0
1
Description
The FRC value is copied to the ICR on the falling edge
of the input capture signal.
The FRC value is copied to the ICR on the rising edge
of the input capture signal.
(Initial value)
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
Bit 0
CCLRA
0
1
Description
The FRC is not cleared. (Initial value)
The FRC is cleared at compare-match A.
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