HD6475328CG Datasheet, PDF (218/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

Figure 10-12 shows this type of contention.
Write cycle: CPU write to lower byte of FRC
T1
T2
T3
ø
Internal address bus
Internal write signal
FRC address
FRC clear signal
FRC
N
H’0000
Figure 10-12 FRC Write-Clear Contention
Contention between FRC Write and Increment: If an FRC increment pulse is generated during
the T3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and
the FRC is not incremented.
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