HD6475328CG Datasheet, PDF (17/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

C-7 (d) Schematic Diagram of Port 7, Pins P74, P75 and P76 ····················································421
C-7 (e) Schematic Diagram of Port 7, Pin P77 ··········································································422
C-8 Schematic Diagram of Port 8 ·························································································423
C-9 (a) Schematic Diagram of Port 9, Pins P90 and P91 ···························································424
C-9 (b) Schematic Diagram of Port 9, Pins P92, P93 and P94 ····················································425
C-9 (c) Schematic Diagram of Port 9, Pin P95 ··········································································426
C-9 (d) Schematic Diagram of Port 9, Pin P96 ··········································································427
C-9 (e) Schematic Diagram of Port 9, Pin P97 ··········································································428
E-1 Reset during Memory Access (Mode 1) ········································································435
E-2 Reset during Memory Access (Mode 1) ········································································436
E-3 Reset during Memory Access (Mode 2) ········································································438
E-4 Reset during Memory Access (Mode 2) ········································································439
E-5 Reset during Memory Access (Mode 3) ········································································441
E-6 Reset during Memory Access (Mode 3) ········································································442
E-7 Reset during Memory Access (Mode 4) ········································································444
E-8 Reset during Memory Access (Mode 4) ········································································445
E-9 Reset during Memory Access (Mode 7) ········································································446
E-10 Reset during Memory Access (Mode 7) ········································································447
G-1 Package Dimensions (CP-84) ························································································451
G-2 Package Dimensions (CG-84) ·······················································································451
G-3 Package Dimensions (FP-80A) ······················································································452
Tables
1-1 Features ······························································································································2
1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) ···········································8
1-3 Pin Arrangements in Each Operating Mode (FP-80A) ····················································12
1-4 Pin Functions ···················································································································16
2-1 Operating Modes ·············································································································23
2-2 Mode Control Register ····································································································29
3-1 Interrupt Mask Levels ······································································································36
3-2 Interrupt Mask Bits after an Interrupt is Accepted ··························································36
3-3 Initial Values of Registers ································································································41
3-4 General Register Data Formats ························································································42
3-5 Data Formats in Memory ·································································································43
3-6 Data Formats on the Stack ·······························································································44
3-7 Addressing Modes ···········································································································46
3-8 Effective Address Calculation ·························································································47
3-9 Instruction Classification ·································································································50
3-10 Data Transfer Instructions ·······························································································52
3-11 Arithmetic Instructions ····································································································53
3-12 Logic Operation Instructions ···························································································54