HD6475328CG Datasheet, PDF (132/459 Pages) Hitachi Semiconductor – Manual Gives a Hardware Description

IRQ 0
IRQ 1
Interrupt controller
DTEA
DTEB
DTEC
DTED
Internal data bus
DTC request
DTC
DTMR
DTSR
DTDR
DTCR
RAM
Register
information table
0
Register
information table
1
DTMR: DT Mode Register
DTSR: DT Source Address Register
DTDR: DT Destination Address Register
DTCR: DT Count Register
DTEA to DTED: DT Enable Register A to D
Figure 6-1 Block Diagram of Data Transfer Controller
6.1.3 Register Configuration
The four DTC control registers are listed in table 6-1. These registers are not located in the
address space and cannot be written or read by the CPU. To set information in these registers, a
program must write the information in a table in memory from which it will be loaded by the
DTC.
Table 6-1 Internal Control Registers of the DTC
Name
Data transfer mode register
Data transfer source address register
Data transfer destination address register
Data transfer count register
Abbreviation
DTMR
DTSR
DTDR
DTCR
Read/Write
Disabled
Disabled
Disabled
Disabled
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